Conventionally, a multiprocessor system which is an information processing apparatus that executes a plurality of tasks in parallel by using a plurality of processors has been used widely as a technique for improving a performance of a computer and executing various tasks.
In the multiprocessor system, there is a case in which data updated by a certain processor remains in a cache memory and the latest data is not present in a main storage device. When another processor tries to refer to or update the data in this case, there is a possibility that a coherence of data (data coherence) cannot be maintained and a correct result cannot be obtained. To prevent the circumstance, a memory access control by using directory information is performed in the multiprocessor system, for example.
Specifically, data stored in each cache memory and the main storage device is associated with directory information which indicates a state of the data (whether or not the data is updated, for example). Then, a memory controller as a memory control apparatus that controls a data transfer between the cache memory and the main storage device determines whether the latest data is present on the main storage device or on any cache memory of other processors with reference to the directory information. By this, each processor can access the latest data at any time and the data coherence can be maintained.
Moreover, another multiprocessor system provided with a directory cache that manages directory information of data stored in a main storage device separately from the main storage device has been developed in recent years. In the multiprocessor system, a memory controller becomes free from a necessity of accessing the main storage device point by point for checking a state of the data stored in the main storage device and the number of accesses to the main storage device is reduced, so that a hi-speed data process can be achieved.
However, there has been a case of causing an unnecessary access to the main storage device and thereby causing a burden on a memory band in the conventional memory access controlling method. The memory access controlling method in the conventional multiprocessor system will be explained below specifically.
In the conventional multiprocessor system, data (cached copy) retained in each cache memory may be expressed by states of “MESI” in which a capital letter “M” is an abbreviation for “Modify”, “E” for “Exclusive”, “S” for “Share”, and “I” for “Invalid”, for example. In addition, the directory information of the main storage device and the directory cache may include information which indicates three states of “E”, “S”, and “I” and information which identifies a processor retaining a copy of data stored in the main storage device.
Besides, an entry of the directory cache may be defined by three states, “N” as an abbreviation for “Null”, “C” for “Clean”, and “D” for “Dirty”, for example. Here, the abbreviation “N” indicates that no valid information is present on the directory cache and directory information can be written into an entry defined by this state. The abbreviation “C” indicates that the directory information on the directory cache is the same as that on the main storage device and an entry defined by this state can be purged without rewriting the directory information of the main storage device. The abbreviation “D” indicates that the directory information on the directory cache is different from that on the main storage device and the directory information of the main storage device needs to be rewritten by the information of the directory cache in purging an entry in this state.
Each entry of the directory cache transits from one state to another among the states “N”, “C”, and “D” depending on a kind of accesses processed by the memory controller. Specifically, the memory controller changes a state of an entry from “N” to “D” for example in a case of receiving a “Request To Share” (RTS) or a “Request To Own” (RTO) with respect to data which is not retained in a cache memory of any processor (step S01) as illustrated in FIG. 6. The memory controller changes the state of the entry to “N” in a case of receiving a notification “Eviction” of a cache line corresponding to the entry from a processor or in a case where the entry is purged from the directory cache due to an insufficiency in capacity and the like when the state of the entry is “D” (step S02).
In a case of receiving the “RTS” with respect to a cache line retained in the state “M” by (a cache memory used by) any processor when the state of the entry is “D”, the memory controller changes the state of the entry from “D” to “C” (step S03). In a case of receiving the “RTO” or in a case of receiving the “RTS” with respect to a cache line which is not retained in the state “M” when the state of the entry is “C”, the memory controller changes the state of the entry from “C” to “D” (step S04).
In a case of receiving the notification “Eviction” of a cache line from a processor or in a case where the entry is purged (cleaned out) from the directory cache when the state of the entry is “C”, the memory controller changes the state of the entry from “C” to “N” (step S05 or step S06). Here, an arrow drawn in a heavy line in FIG. 6 indicates an occurrence of an access to the main storage device when the memory controller performs a corresponding process (among processes at steps S02, S03, and S05).
The memory controller then determines whether or not to access the main storage device based on the state of the entry in receiving a request of various kinds from a processor.
Here, a case in which an unnecessary access to the main storage device by the memory controller occurs will be explained specifically with reference to FIG. 7. FIG. 7 is an explanatory view of a memory access controlling method in the conventional multiprocessor system. Here, data (Payload) “aaaaaa” stored at an address X of the main storage device at an initial state is assumed not to be stored in any cache memory and to be retained in the main storage device in the state “I”. The multiprocessor system adopts a directory cache of a write-back system. The write-back system is a system of writing, without writing data in parallel to both of a cache memory and a main storage device in writing the data to the cache memory, the data to the main storage device in the case where the data is purged from the cache memory and the like.
As illustrated in FIG. 7, in a case where a processor A transmits the “RTS” to a memory controller for sharing the data “aaaaaa” stored in the main storage device (step S11), the memory controller requests “Read” with respect to the main storage device (step S12) to obtain the data “aaaaaa” (step S13). The memory controller then transmits the obtained data “aaaaaa” to the processor A (step S14) and the processor A having obtained the data updates directory information of its own cache memory to be “S”. Since directory information of the main storage device is not rewritten at this time point in the multiprocessor system adopting the write-back system, the data “aaaaaa” of the main storage device remains in the state “I”.
On this occasion, the memory controller records “S:Sharer=A” as information of the state of the data “aaaaaa” and a processor which retains the data, and records “address X” as address information at the same time in the directory information of the directory cache. The memory controller then makes a state of an entry corresponding to the data “aaaaaa” “D” since the directory information “S:Sharer=A” on the directory cache and the directory information “I:undefined” is different.
Next, in the case of purging a cache line because the cache line cannot be stored in a cache memory, becomes unnecessary, and the like, the processor A transmits a notification “Eviction” to the memory controller (step S15). The notification “Eviction” is a signal to be transmitted in purging data in the cache memory. The memory controller having received the notification “Eviction” makes the entry corresponding to the data “aaaaaa” in the directory cache null (makes the state transit to the state “N”).
When the state of the entry is “D” on this occasion, the memory controller accesses (performs reading, modifying, and writing in) the main storage device (step S16) since the directory information on the main storage device needs to be written-back to be accorded with the directory information on the directory cache. Here, when the cached copy on the cache memory is not modified and when the directory information of the data “aaaaaa” stored in the main storage device is in the state “I” from the beginning, there is no change in the content (data and directory information) of the main storage device before and after the process of the notification “Eviction”. In other words, the access to the main storage device in this case is unnecessary fundamentally.
However, the memory controller cannot determine the content of the directory information in the main storage device only based on the directory information on the directory cache in the conventional multiprocessor system, thereby performing a memory access despite the fundamental unnecessity.